1. Technical Field
The present invention relates generally to integrated circuit design, and more particularly, to via redundancy based on subnet timing information, a distance of a target via along path from a driving source and/or target via net/subnet characteristic.
2. Related Art
In the semiconductor chip manufacturing industry, defects on silicon products are often difficult to detect and can result in the shipment of products with hidden defects that can result in product failures. A “via” is a hole etched in an interlayer dielectric that is then filled with metal to provide a vertical connection between stacked up interconnect metal lines in a semiconductor chip. Vias are a major cause of yield problems. In terms of detecting problems with vias, some problems are generally easy to detect, such as a totally open via, i.e., one causing an open circuit. Other problems, however, are harder to detect. For example, a partially open via or one having resistance significantly higher than desired is very difficult to detect.
In order to improve yield, via redundancy is usually employed where possible, i.e., where area and layout groundrules permit. However, space in layouts is limited, and it is not always possible to add a redundant via to a given original via. A challenge that the limited number of via redundancy implementations presents is that some problem vias affect performance more than others. Vias having a higher resistance than a desired resistance are particularly challenging. For example, high-resistance vias at the end or destination of a net have significantly less impact on performance. In contrast, high-resistance vias at the beginning or source of a net typically affect performance degradation more than others because of the resistance-capacitance (RC) effects, i.e., delay imposed on nets because of the resistance and capacitance associated with the wires and vias that make up the net, imposed on the nets in question. Unfortunately, conventional post-routing via redundancy algorithms approach each via on a first-come-first-served basis without any regard for its relative importance to the overall system. As a result, if a first via is duplicated and a second via is more significant to performance, but the second via cannot have a redundant mate because the first via's redundant mate is in the way, a defect caused by the second via is allowed to exceedingly affect performance.
In another approach, disclosed in U.S. Pat. No. 6,715,133, redundant vias are prioritized based on which via more current must flow to charge or discharge capacitance. In one form, this approach prioritizes target vias based on an arbitrary counter relative to a source, which is not as accurate as actual distance from the source. In addition, this approach ignores clock nets and does not allow for subnet evaluation, each of which makes the evaluation not fully comprehensive.
In view of the foregoing, there is a need in the art for an intelligent algorithm that weighs the importance of a redundant via relative to subnet timing information, a distance of a target via along a path from a driving source and net characteristics, and uses that information as it adds redundant vias.